The present invention relates to a multi-die package, and more particularly to a multi-die package for reducing the current consumption.
Recently, electronic apparatuses are much leaner and lighter in accordance with the developments of the semiconductor industry and the requirements of a user. One technique for creating leaner and lighter electronics is a multi-chip packaging technique.
The multi-chip packaging technique means a technique for packaging a plurality of semiconductor chips in one package. Here, a method of using the multi-chip package has more advantages than a method of using a plurality of packages which have respectively one semiconductor in view of miniaturization, light weight and packaging area.
Generally, one of the chips in the multi-chip package is selected in response to a selecting signal in its operation. In this case, the chip not selected does not operate during the operation of the selected chip.
FIG. 1 is a block diagram illustrating a common double die package.
In FIG. 1, the double die package where two memory chips are packaged includes a first die or chip 100A and a second chip 100B. Here, the second chip 100B has the same constitution as in the first chip 100A.
The first chip 100A includes a memory circuit 110 and a power supply circuit 130 for supplying power to the memory circuit 110. Here, the memory circuit 110 has a surrounding circuit for operating semiconductor chip and memory cells.
The memory circuit 110 has a memory cell array 111, a X decoder circuit 112, a page buffer circuit 113, a Y decoder circuit 114, a buffer 115, an I/O 116, an address register/counter 117, an operation control and high voltage generating circuit 118, a command interface logic 119, a command register 120 and a data register 121.
The power supply circuit 130 includes a standby power circuit 131, an active power circuit 132, a reference power circuit 136 and a power level sensing circuit 137.
The reference power circuit 136 has a standby mode circuit 134 and an active mode circuit 135.
The second chip 100B has the same constitution as in the first chip 100A.
The first chip 100A and the second chip 100B operate selectively in response to a chip selecting signal CE#. Here, in the case that the chip selecting signal CE# having a low level is transmitted, a corresponding chip operates.
When the chip selecting signal CE# having a low level is transmitted to one of the dice 100A and 100B, a corresponding chip is in an operation mode. However, when the chip selecting signal CE# having a high level is provided to one of the dice 100A and 100B, a corresponding chip operates in a standby mode as a non-select chip.
In the case that the chip selecting signal CE# having a low level is transmitted, circuits which operate using a minimum standby power are converted into main circuits. Then, an active power is applied to the circuits, and so the circuits operate.
In the active mode, the active power circuit 132 provides an active voltage. Additionally, power is applied to the active power circuit 132, the I/O 116, the buffer 115, the address register/counter 117, the command interface logic 119, the command register 120, the data register 121, the X decoder circuit 112 and the Y decoder circuit 114 during data input, and so the circuits 132, 116, 115, 117, 119, 120, 121, 112 and 114 operate.
Moreover, the operation control and high voltage generating circuit 118, the X decoder circuit 112, the page buffer 113 and the Y decoder circuit 114 operate in the above operation condition.
In the standby mode, the standby power circuit 131 provides a standby voltage. In this case, only power level sensing circuit 137 operates to sense a voltage level of the command interface logic 119.
In the case that a chip to which the chip selecting signal CE# having a low level is transmitted operates as mentioned above, chip selecting signals CE# for operating each of the die 100A and 100B are required in the package having the first chip 100A and the second chip 100B as shown in FIG. 1. However, only one chip selecting signal CE# is usually employed in a multi-die package so as to control the operation of the multi-die package.
In the case that the multi-die package operates in accordance with the common chip selecting signal CE#, the active power is also applied to the non-select chip that is not operated. That is, a current is unnecessarily consumed. Accordingly, the multi-die package where the common chip selecting signal CE# is transmitted has an concurrent operation function for operating the non-select chip together when a ready/busy signal R/B# of the chip being operated in accordance with the chip selecting signal CE# is converted into a low level, i.e. the chip is busy.
FIG. 2 is a timing diagram illustrating an operation of the multi-die package in FIG. 1.
FIG. 2 shows the operation of the multi-die package having the concurrent operation function in FIG. 1. In particular, FIG. 2 illustrates an operation timing diagram 210 of the first chip 100A and an operation timing diagram 220 of the second chip 100B.
Referring to FIG. 2, the chip selecting signal CE# is simultaneously transmitted to the dice 100A and 100B, and so the first chip 100A starts to operate. Then, in the case that the ready busy signal R/B# of the first chip 100A is converted into a low level, the second chip 100B should operate.
In other words, in the case that an operation command is provided to the second chip 100B during the ready busy signal R/B#=low of the first chip 100A, the second chip 100B senses the operation command, and then the second chip 100B operates in response to the operation command. In particular, in the first chip 100A selected to be operated, the active power circuit 132, the active mode circuit of the reference power circuit 136 and the power level sensing circuit 137 operate in accordance with the active mode. Whereas, in the standby mode, the standby power circuit 131, the standby mode circuit 134 of the reference power circuit 136 and the power level sensing circuit 137 in the first chip 100A operate.
The non-select second chip 100B which did not operate receives the operation command during the ready busy signal R/B#=low of the first chip 10A.
However, since the power is not applied to the address register/counter 117, the command interface logic 119, the command register 120 and the data register 121 which senses the operation command, a problem that the operation command is not sensed may occur.